The present publication is based on Japanese Application Serial No. 6-325145, filed Dec. 27, 1994, the disclosure of which is incorporated herein by reference.
In fabricating a circuit board, techniques for forming a conductor on the surface of the circuit board are roughly divided into three. The first is a method called the subtractive method. In this method, a metal foil is formed on the surface of an insulating material and then an etching resist corresponding to the circuit is formed on the metal foil. Then the unnecessary part of the metal foil is removed by wet etching, thereby forming the circuit board. The second method involves forming a circuit by etching after forming a conductor on the surface of an insulating material by sputtering. The third is called the additive method. In this method, the surfaces of an insulating material other than those intended to carry the circuit, after treating with palladium, are covered with a plating-resistant resist and then a conductor is deposited on the portion not covered with the plating-resistant resist.
On the other hand, in the formation of multilayer wiring printed circuit boards (SLC), the technique used involves treating the surface of an insulating material with palladium, depositing a thin conducting layer on the whole surface of the insulating material by electroless plating and then forming a conductor circuit by etching. In practice, after the above deposit of an electroless plating, electroplating is performed to increase the thickness of the conducting layer. In these processes, palladium acts as a catalyst in electroless plating and is effective for easily forming a conductor layer. However, palladium is extremely difficult to dissolve in a normal etching solution and remains after etching in devices having electroless plated and electroplated conductors.
Recently, electroless gold plating, electroless palladium plating, and the like have been frequently used in the surface treatment of pads for the joining of parts. If palladium remains on the surface of the insulating material, gold or palladium is deposited on unintended portions of the insulating material by catalytic action of the residual palladium, thereby generating a short circuit.
It is an object of the present invention to provide a circuit board capable of preventing a short circuiting attributable to catalytic metals, such as palladium, as well as a fabrication method therefor.